The present application relates to a semiconductor fabricating technology, and more particularly, to a gate of a semiconductor device and a fabricating method thereof.
A peripheral circuit of a DRAM employs a dual-poly gate in which a gate of an NMOS transistor is formed as N-type polysilicon and a gate of PMOS transistor is formed as P-type polysilicon. Unlike some circuits that employ N type polysilicon gates for both of NMOS and PMOS transistors, a surface channel can be formed by forming the gate of the PMOS transistor as P type polysilicon. This technology has various advantages that include reduction of short channel effect, improvement of a drain saturation current Idsat for the same threshold voltage Vt, improvement of sub threshold voltage (Sub threshold slop), and improvement of drain induced barrier lowering (DIBL). Also, the P type polysilicon gate improves a retention time and enables to fabricate a DRAM device having low power and high performance.
In case of forming a recess gate in a cell region in order to employ the dual polysilicon gate, in-situ doping is performed to uniformly sustain concentration of impurities in the recess when polysilicon is formed. Accordingly, a counter doping process is performed to convert a gate polysilicon of a PMOS transistor to P-type polysilicon by doping P-type impurity only at the gate polysilicon of the PMOS transistor after forming N type polysilicon when gates of NMOS and PMOS are formed. Therefore, it is necessary to have high dose to perform counter-doping to convert N doped polysilicon to P type polysilicon.
Some methods include fabricating the dual polysilicon gate by forming a metal electrode over the polysilicon after performing high dose counter doping for converting PMOS to P type polysilicon after forming N type polysilicon.
However, if the high dose counter doping is performed, silicon and dopants (including counter-doped dopants and in situ doped-dopants generated when the polysilicon is deposited) may be present at an interface of the polysilicon and the metal electrode at approximately the same ratio. This same ratio is because dopants are concentrated to a surface when the counter doping is performed and uniformly-doped N type impurities are also gathered to the surface due to the influence of the counter doping. Therefore, the dopants are further concentrated at the interface.
Accordingly, because the silicon is not recrystallized and the dopants do not fully function as dopant, this layer becomes a damage layer. Since such a damage layer functions as a dielectric at the interface of the polysilicon and the metal electrode, the damage layer causes signal delay.
FIG. 1 depicts a Transmission Electron Microscopy (TEM) picture illustrating polysilicon after counter doping is performed according to the related art.
As shown in FIG. 1, polysilicon is converted to amorphous silicon if counter doping is performed, and the amorphous silicon is recrystallized through a following thermal process. However, since the silicon and the dopants are present at the interface of the silicon at about the same ratio, the silicon is not recrystallized. The not-recrystallized silicon forms a damage layer and may cause a signal delay problem.